1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to short-channel transistor source and drain regions which are less susceptible to diffusion and allow improved control over transistor characteristics, and a method for fabricating these source and drain regions.
2. Description of the Relevant Art
Fabrication of a metal-oxide-semiconductor (MOS) integrated circuit involves numerous processing steps. A gate dielectric, typically formed from silicon dioxide ("oxide"), is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form a source and drain. The channel of the transistor is located under the gate dielectric, between the source and drain. A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many modern day processes employ features, such as gate conductors and interconnects, which have less than 0.3 .mu.m critical dimension. As feature size decreases, the sizes of the resulting transistor and the interconnect between transistors also decrease. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
Such feature size reduction can place severe demands on reliable operation of the resulting transistors. For example, reduction in the transistor gate length can result in very high electric fields at the drain end of the transistor channel, unless the drain-to-source voltage used in operating the transistor is reduced by a corresponding amount. High electric fields can give rise to undesirable "hot carrier" effects in transistors, including avalanche breakdown at the drain/substrate junction and injection of carriers into the gate dielectric. These hot-carrier effects are typically mitigated by the use of dielectric sidewall spacers adjacent to sidewalls of the gate conductor. A relatively shallow impurity distribution, known as a lightly-doped drain (LDD) distribution, is first ion-implanted into the substrate using the gate conductor as a mask. The dielectric sidewall spacers are then formed, such that LDD portions adjacent the channel region are covered by the sidewall spacers. A deeper and somewhat more heavily doped impurity distribution is then implanted into the substrate using the gate conductor and sidewall spacers as a mask.
A cross-sectional view of an idealized MOSFET structure using LDD regions in the source and drain is shown in FIG. 1. Gate conductor 14 is formed over gate dielectric 12 on semiconductor substrate 10. LDD portions 18 are formed within substrate 10 before formation of dielectric sidewall spacers 16. Deep source/drain portions 20 are formed by implantation into substrate 10, aligned to sidewalls of spacers 16. Portions 18 and 20 are of opposite impurity type than substrate 10. For an n-channel transistor, for example, portions 18 and 20 are n-type, while substrate 10 is p-type. The doping of LDD portions 18 is somewhat lower than that of portions 20, resulting in a lowered electric field associated with the p-n junction at the drain end of the MOSFET channel, thereby reducing the severity of hot-carrier effects. Furthermore, the small junction depth of LDD portions 18 reduces encroachment into the channel of the depletion region associated with the drain/channel p-n junction. This reduced depletion region encroachment may minimize other undesirable effects associated with short-channel transistors, as discussed in more detail below. The heavier doping and deeper extent of source/drain portions 20 aids in making contact to the source/drain regions.
A more realistic representation of a MOSFET with LDD regions is shown in FIG. 2. The transistor of FIG. 2 differs from that of FIG. 1 in that LDD portions 18 are partially below gate conductor 14, rather than being aligned under spacers 16. In addition, source/drain portions 20 are partially below spacers 16, rather than being aligned outside of spacers 16. This change in the position of portions 18 and 20 from the as-implanted distributions is a result of diffusion of the implanted impurities during the subsequent fabrication steps. The speed and extent of this diffusion is enhanced by the presence of structural defects introduced into substrate 10 during ion implantation of portions 18 and 20. Such defect-enhanced diffusion is also referred to as "transient-enhanced diffusion" (TED), wherein defects or other incidences of nonuniform structure (such as doping nonuniformities) are termed "transients". The movement of source/drain portions 18 and 20 undesirably decreases the effective length of the channel to a value smaller than that defined by the length of gate conductor 14. Furthermore, the defect-enhanced diffusion of portions 18 and 20 may not occur in a reliable, repeatable way, making predictable device fabrication difficult.
An additional problem associated with the overlap of gate conductor 14 and LDD portions 18 in FIG. 2 is an increased overlap capacitance between the gate and the source or drain. This overlap capacitance, along with other capacitances and resistances associated with the transistor structure, contributes to an RC time constant which characterizes delays associated with signal propagation through a transistor circuit. Fabrication of a circuit with increased RC time constants lowers the speed at which the circuit can operate by increasing the time needed, for example, for a circuit output voltage to respond to a change in input voltage. The undesirable diffusion of LDD portions 18 into the channel of the transistor of FIG. 2 can be reduced somewhat by keeping the doping of LDD portions 18 relatively low. However, this places an undesirable constraint on the doping of the LDD regions. The term "lightly-doped drain" implies a low doping in the LDD regions, and this has been the case historically. In current high-performance MOSFETs, however, the "LDD" region doping level is often within an order of magnitude of the doping level of the deep, heavily-doped source/drain portions. This increased LDD doping level reduces the series resistance of the LDD region, thereby increasing the transistor drive current. Lowering the doping level of the LDD region to mitigate the defect-enhanced diffusion of ion-implanted LDD regions may therefore increase the LDD series resistance and lower the transistor drive current.
In addition to the hot-carrier effects described above, other undesirable effects are associated with reduced feature sizes, and particularly shortened channel lengths, in MOSFETs. Some of these short-channel effects are associated with encroachment into the channel area of depletion regions from the drain/channel and source/channel p-n junctions. High electric fields within the drain/channel depletion region are associated with the hot-carrier effects described above. Under some conditions in a short-channel device, the depletion regions associated with the source/channel and drain/channel junctions may actually become joined in an area below the transistor channel. This joining of depletion regions, known as "punchthrough", creates a path for drift of carriers from the source to the drain other than the intended transistor channel, and can lead to a loss of control of the channel by the transistor gate. Another short-channel effect related to the drain/channel and source/channel depletion regions is threshold voltage reduction, described in more detail below.
Feature size reduction drives a reduction of overall transistor dimensions and operating voltages known as "scaling". As gate conductor widths decrease, for example, other device dimensions must also decrease in order to maintain proper device operation. Early MOSFET scaling techniques involved decreasing all dimensions and voltages by a constant scaling factor, to maintain constant electric fields in the device as the feature size decreased. This approach has given way to more flexible scaling guidelines which account for operating characteristics of short-channel devices (devices having channel lengths less than about 1 micron). For example, a maximum value of MOSFET subthreshold current can be maintained while feature sizes shrink, by decreasing any or all of several quantities, including gate oxide thickness, operating voltage, depletion width, and junction depth, by appropriate amounts.
For scaling to submicron feature sizes, device dimensions and voltages are generally not each decreased by the same factor. One dimension which has been steadily decreasing, for example, is gate oxide thickness. A major factor driving reduction of gate oxide thickness is the increased transistor drain current realized for a reduced gate dielectric thickness. Higher transistor drain currents are desirable because they allow each transistor to drive a greater number of other transistors, and can result in increased switching speeds. A device parameter which has not decreased significantly in conjunction with feature size reduction, on the other hand, is device threshold voltage, V.sub.T. MOSFET V.sub.T has been relatively constant at about 0.7 volts (or slightly less), and is projected to remain at about this value as feature sizes continue to decrease. A decrease in threshold voltage below this value may be undesirable because subthreshold leakage current for zero gate voltage (in the case of an enhancement-mode transistor) is increased as threshold voltage is decreased. The design value of V.sub.T has therefore remained relatively constant, and device scaling has involved reduction of other quantities, such as junction depth and supply voltage, by varying amounts.
Maintaining a particular design value of V.sub.T as channel lengths decrease, however, presents certain challenges. For a given oxide thickness and substrate doping, V.sub.T tends to decrease as channel length decreases, for channel lengths smaller than about 2 microns. As used herein, a decrease in V.sub.T refers to a V.sub.T which becomes less positive or more negative in the case of an n-channel device, or a V.sub.T which becomes less negative or more positive in the case of a p-channel device. This decrease in V.sub.T occurs because the effect of the source and drain depletion regions on the charge controlled by the gate becomes increasingly important as channel length decreases. An exemplary enhancement-mode MOSFET biased into inversion is shown in FIG. 3. Gate dielectric 12 and gate conductor 14 are formed upon semiconductor substrate 10, while source 24 and drain 22 are formed within substrate 10 on either side of gate conductor 14. Before free charge in inversion region 26 is induced by a voltage applied to gate conductor 14, a depletion region 28 (having a boundary marked with a short-dashed line) is formed in substrate 10 below gate dielectric 12. The threshold voltage V.sub.T which must be applied to gate 14 to turn on the transistor includes the voltage needed to establish depletion region 28 and that needed to induce the carriers in inversion region 26.
As shown in FIG. 3, parts of depletion region 28 are formed by drain depletion region 30 arising from the drain-to-substrate junction and source depletion region 32 arising from the source-to-substrate junction. Boundaries of source and drain depletion regions 32 and 30 are marked by long-dashed lines in FIG. 3. This leaves only the charge in shaded depletion region 34 to be induced by the gate voltage, which reduces the voltage needed to turn on the transistor as compared to that predicted using depletion region 28. For given doping levels and oxide thickness, V.sub.T decreases as the channel length decreases because the fraction of the depletion region under the channel which is contributed by the source and drain regions becomes larger with decreasing channel length.
One possible way to counteract both the decrease in V.sub.T and the possibility of punchthrough as channel length is decreased is to use a higher background channel doping level for short-channel devices. In the case of an n-channel device, for example, the substrate doping in the channel region would be made more p-type. A higher voltage would then be needed to create an inversion layer and turn on the transistor. A drawback to this approach is that higher doping levels in the channel region result in decreased carrier mobility, and thereby reduced transistor drive current. Furthermore, increasing the channel doping enough to prevent punchthrough may result in an increase in V.sub.T above its design value. Such a V.sub.T increase may also undesirably reduce transistor drive current.
An alternative approach is to locally increase the background doping at the source and drain ends of the channel, without increasing the doping in the central portion of the channel. This increased doping in the vicinity of the source/channel and drain/channel junctions may decrease the source and drain junction depletion widths at the channel edges. Such a reduction in source and drain depletion widths lessens the encroachment of the source and drain depletion regions into the area underlying the transistor gate, thereby reducing punchthrough and lessening the reduction in V.sub.T exhibited by the short-channel transistor. The more heavily-doped region at the channel ends is often called a "halo". Such halos are generally formed using angled ion implants which direct the implanted impurities below the edges of the gate conductor.
A cross-sectional view of an idealized MOSFET formed with a halo implant is shown in FIG. 4. The transistor of FIG. 4 is similar to that of FIG. 1, except that halo regions 36 are included at the source and drain ends of the transistor channel. Unlike source and drain portions 18 and 20, halo regions 36 are doped with the same impurity type as substrate 10. For an n-channel transistor, substrate 10 is p-type, and regions 36 are also p-type, and more heavily doped than substrate 10. In practice, there are several problems with the implanted halo formation of the transistor in FIG. 4. In a similar manner as described above for LDD formation, the use of ion implantation can cause structural defects which lead to enhanced diffusion of halo and source/drain impurities into the channel region. Furthermore, accurate placement of the halo regions is complicated by strong dependence of the position on factors such as implant energy, implant dose, and thickness of surface oxides. The implantation process is also very time-consuming because the wafer must be rotated in 90 degree increments between implants to allow introduction of the halo impurities below each side of the gate conductor perimeter. In addition, because the angled implants are directed toward the sidewalls of the gate conductor, damage to the gate conductor may result.
It would therefore be desirable to develop a method for reducing diffusion of source/drain features such as LDD regions and halos. The desired method should allow accurate placement of source/drain regions and should not cause increased resistances in the transistor.